The present invention relates to the methods of converting analog electric signals into a stream of binary data, to be implemented with Integrated Circuit technology in general, and silicon Conplementary Metal Oxide Semiconductor (CMOS) circuits and technology in particular.
The fundamental problem of an analog-to-digital converter (ADC) is to determine for a given input voltage value “Vin” a corresponding digital binary value, “Bin”. For example, an input voltage value of 1 volt might be encoded in binary as 00001000, and the value 1.25 volt might be encoded as the binary value 00001010. The process of assigning binary values to particular voltage values and voltage ranges is called quantization.
The conventional characterization of ADCs relies, mostly, on a few figures of merit, namely:
(a) The conversion rate: This metric, defined in number of samples per second (SPS), defines how fast can an individual conversion be performed;
(b) The resolution: This metric defines how many bits are used to characterize in the digital domain an input voltage value. It is defined as the number of quantization bits, or bit depth;
(c) The dynamic range: This metric defines the range of input voltage values that can be captured by the resolution of the ADC, and it is intimately connected with the maximum and minimum accepted input voltage levels, and the number of bits.
In terms of implementation of ADCs there are three basic methods, which are briefly described herein after. There are many schemes for conversion of analog signals to a binary digital representation. A conventional ADC uses a “Sample-and-Hold” (S&H) circuit to “capture” an “instataneous” value of the input signal. The “captured” value is the input voltage to be converted. The time interval until the next sample is captured, defines the conversion rate. The S&H circuit usually consists of a capacitor and a circuit to hold steady the electrical signal being digitized by the ADC circuitry.
ADC conversion methods can be divided into three main classes, namely direct methods, feedback methods and integrating methods. These methods have distinct power consumption, accuracy and sampling rate metrics.
In the direct methods, the ADC circuitry directly uses the input signal and compares it against a set of predefined reference voltage levels. For example, in a parallel or flash ADC implementation with a quantization of N-bits, the input voltage is compared against a set of 2N−1 comparators. The output of each comparator directly defines a digital value for the input signal for a specific bit position. This is an extremely fast method but with increasingly prohibitive costs for larger numbers of conversion bits as for N bits, the implementation must have an electrical mesh with 2N resistors and 2N−1 comparators. This method is also very prone to noise problems.
Also in this category are the sub-ranging ADCs, sometimes also called “pipelined ADC architectures”. In the sub-ranging scheme, N conversion ADCs with B bits of resolution are cascaded to attain N×B bits of resolution. The idea is that each of the ADC successively refines the conversion; the first ADC converts the higher order B most significant bits; the next ADC the next B bits and so forth. At each stage the input signal is subtracted with the analog values corresponding to the bits resolved at that point in the cascade, so that the next set of B bits can be converted. This scheme requires equal numbers of ADCs and digital-to-analog conversion circuits along with analog signal subtractor circuits. A potential drawback is the need for analog subtraction, which is prone to noise problems. Although quite high throughput can be attained, the latency of conversion, i.e., the time taken for a single conversion to be completed, is relatively low.
In the feedback methods, the binary representation for the signal is attained indirectly by comparing a running reference signal against the input signal. When the two signals match, the conversion stops, and the corresponding binary representation for the running reference signal is reported. Examples of this class of conversion schemes include the “single-slope” and “dual-slope” methods.
One version of this counter-based approach is the tracking or “Successive Approximation” Conversion. This method, rather than attempting to generate a full binary representation of the input voltage at once, relies on a sequence of steps to derive the full binary value. A register is connected to a Digital-to-Analog Converter (DAC) that is connected to a comparator that checks the output of the DAC against the input signal. First, the method determines the higher-order bit or bits, followed by the determination of the lower-order bits, until the fill binary value has been determined The conversion is done by successively setting the most significant outstanding untested bits of the register. A given bit of the register is set to 0 if the output of the DAC for that setting surpasses the input signal as noticed by the comparators output. If not the bit of the register is set to 0 and the conversion advances to the next bit of the register.
There are numerous implementations of the successive approximation method. Some rely on a comparison of voltages, either the input voltage or a reference voltage generated by a DAC. The comparisons proceed using a binary search strategy until all bits are resolved. Another commonly used approach, as popularized by the Delta-Sigma method, consists of using a digital up/down counter in which the value of the counter is either incremented or decremented, based on the voltage difference between the input signal and the analog conversion of the value of the digital counter by an auxiliary DAC. Overall, this method of tracking the input signal trades-off speed of tracking for precision of conversion, since the counter cannot keep up with very fast changing signals.
Another version is the “Voltage-to-Time” or “Voltage-to-Frequency” conversion approach. With this method, the input binary digital value corresponding to the input analog voltage is determined by the value of a digital counter. In the voltage-to-time conversion approach, the counter is allowed to count from 0 up to the time when the analog value, i.e., the result of the digital-to-analog conversion of the counter value, exceeds the input analog voltage. In the Voltage-to-Frequency conversion the counter is provided with a train of digital pulses whose number per unit of time (i.e., frequency) is proportional to the value of the input voltage. The number of pulses generated for a defined time interval, determines the binary digital value corresponding to the input analog voltage. The counter conversion method consists of a single analog comparator. At one input of the counter we have the input signal. The other input is connected to an analog signal generated by a DAC circuit that in turn is connected to a binary digital counter. The counter is left running until the output of the DAC equals or surpasses the input signal. When this happens the comparator's output becomes active stopping the binary counter and therefore the conversion. Of all the methods mentioned above, this is the slowest but also the most precise, making it very attractive when raw speed is not an issue. In integrating methods, the quantitation is accomplished by converting the input signal amplitude into a time interval to be measured subsequently. The single slope method, is the simplest of the methods in this class, and consists of loading a capacitor with the input signal voltage and using a counter that is stopped when the capacitor voltage reaches a predefined reference value. The dual-slope conversion method is a version of this method with better insensitivity to variation of the parameters relevant to capacitor design. While these methods are highly linear and are good at rejecting input noise, they are quite slow. Another scheme is the first order Delta-Sigma. This scheme consists of a Delta-Sigma modulator, a digital filter, and a decimator and relies on the spectral effects of over-sampling to provide improvements of the signal-noise-ratio (SNR) of the overall conversion.
Several refinements of these methods exist For example, current state-of-the art pipelined conversion implementations use a variant of the successive approximation methods, that allows each of a many conversion stages to focus solely on converting a portion of the input voltage (rather than the full amplitude), thereby increasing the throughput of the conversion at the price of higher overall conversion latency. As for the Delta-Sigma methods, other variants use multiple bits rather than a single increasing/decreasing bit as mentioned above.
In terms of traditional applications, “Flash ADCs” are used for applications when raw speed is of paramount importance, such as for the acquisition of short bursts or fast changing signals, i.e., high-frequency signals. “Voltage-to-Frequency” methods are used when precision is more important than speed.
Depending on the application, some methods are preferable to others. For example, in image-sensors for digital photography, if the A-to-D conversion had to be done serially for all pixels in the image-sensor, then either precision or pixel count would have to be traded-off. However, 2D arrays of pixels are highly suitable for massive parallelization, in which each column can have its own ADC. A further step in parallelization is to have “in-pixel ADC”, provided the circuit area for the ADC is reasonable compared to the total area for the pixel. This is the type of application in which “Voltage-to-Frequency” methods have been favored, partly due to their precision, and partly due to their low transistor count. In the field of image-sensors, the conventional faster methods of A-to-D conversion are inadequate due to their high implementation cost in terms of the overall number of transistors.
Overall conventional schemes rely on the fact that the input signal, a voltage, has to be held constant for a short period of time. To this effect, conventional architectures have a sample-and-hold (S&H) circuit. The S&H circuit consists essentially of a capacitor to charge up and hold the input voltage for as long as it takes to convert this voltage to a binary digital representation. In addition, the implementation defines the conversion rate in a rather rigid fashion (hardwiring), with the latter being dependent on the time the S&H circuit holds the input voltage value. The holding interval is the time of conversion, and defines a time base for the remainder of the operations in the ADC.
Another fundamental aspect of the current architectures is that, the number of bits dedicated to the conversion, is also predefined in a rigid fashion. For example in the Parallel or Flash ADC, the number of steps in the ladder defines the number of bits. In the successive approximation approach, the DAC also needs to have a predefined number of bits. In conventional implementations of Voltage-to-Frequency conversion methods, the digital counters have also a predefined number of bits.
Once defined, these two fundamental parameters, sampling/conversion time and number of bits, constrain the current designs and do not allow for a flexible digitally programmable ADC. Therefore it is not possible to manage the available bandwidth of the ADC, to adapt it to changing characteristics of the input signal and/or requirements for the conversion. The ADC architecture described this document is very flexible. It combines the precision of a voltage-to-frequency conversion for very small differential signals, with an extrapolation scheme for large amplitude input signals.
With respect to the fabrication technologies employed to manufacture integrated circuits, and especially CMOS technology, it is well known that historically the main driving forces behind “Moore's Law” have been the purely digital circuits, such logic and memory. The incorporation of analog circuit elements into an IC requires a more stringent control of the fabrication processes in order to reduce leakage currents and the variability of the electrical parameters of the analog components. Depending on the application, it may even be necessary to include more active elements, such as bipolar transistors, in which case extra process steps need to be added to the fabrication flow. In addition, some of the extra process steps interact with others, leading to an extensive and expensive fine-tuning of the entire fabrication process. It is then not surprising that the leading edge Analog CMOS process technology usually lags one or two generations behind the leading edge Digital CMOS process technology available from the same vendor (silicon foundry). Furthermore, the laws of CMOS scaling dictate the operating voltage to roughly scale in the same proportion to the physical dimensions of the MOSFETs (this is called “constant electric field scaling”). This presents a serious problem to analog circuit design because the scaling of noise level does not follow the scaling of the operating voltage, and therefore die signal to noise ratio is reduced. It is very questionable if analog circuit design can be practical for operating voltages of 1 volt and below.
It is therefore highly desirable to have ADC designs, which do not require analog circuit elements, such as adders and subtractors, and hence could be fabricated with the leading edge Digital CMOS process technologies. There are many advantages in using a CMOS process technology which is two generations more advanced, including the critical issue of making unnecessary the fabrication of bipolar transistors, due to the much better high-frequency performance of the more advanced (smaller) MOSFETs. Other advantages include, more sophisticated digital circuitry, which may enable the co-integration of functionalities that would otherwise require extra ICs; the possibility of operation at a lower voltage with the consequent lowering of power dissipation, with beneficial impact on the heat removal and battery lifetime; smaller transistors also mean more ICs per wafer and thus lower production costs; etc.